Various types of display devices are either available or being proposed. One such type of display device is an organic light emitting diode (OLED) display device. An OLED is a special type of light emitting diode (LED) in which the light emissive layer is formed of a thin film of organic compounds. An OLED display device has a matrix of pixels, where each pixel includes an OLED and other circuitry.
Referring to FIG. 1, a circuit diagram of a conventional pixel 10 is shown, which includes an organic light emitting diode (OLED) D1, capacitors C1 and C2 and transistors Q1-Q4. The transistors Q1 Q4 are p-type thin film transistors (TFTs). The transistor Q2 is for outputting an operational current I1 to the OLED D1. The OLED D1 has a negative end coupled to a source voltage Vss1 and a positive end coupled to a drain of the transistor Q1. The transistor Q1 has a gate for receiving an activation/deactivation signal (MRG) and a source coupled to a drain of the transistor Q2 and a source of the transistor Q4. A gate of the transistor Q4 is for receiving a reset signal RST.
The transistor Q2 has a source coupled to a source voltage Vdd1 and one end of the capacitor C2, and a gate coupled to the other end of the capacitor C2, a drain of the transistor Q4 and one end of the capacitor C1. The capacitor C1 has the other end coupled to a source of the transistor Q3. The transistor Q3 has a gate for receiving a scan signal SCT(n) and a drain for receiving a DAT signal.
Referring to FIG. 2, a timing diagram of a conventional pixel is shown. In order to compensate for the effect of a transistor threshold voltage on the operational current, the above MRG signal, reset signal RST, scan signal SCT(n) and DAT signal operate according to a timing sequence as shown in FIG. 2. The sequence of signals is used for successively enabling the transistors Q1˜Q4 and resetting a gate voltage Vg2 of the transistor Q2 to be (Vdd1−Vth) in a period T1.
When the gate voltage Vg2 of the transistor Q2 is reset to be (Vdd1−Vth), the drain of the transistor Q3 receives a DAT signal, which is a to-be-written pixel data voltage Vdata, in a period T2. After the period T2, the transistor Q2 outputs an operational current I1 to the OLED D1. Because the gate voltage Vg2 of the transistor Q2 is reset beforehand to be (Vdd−Vth), the operational current I1 will not be affected by the threshold voltage when outputted by the transistor Q2.
The period length of the pixel data voltage Vdata is equal to the period T2, but the period length of the scan signal SCT(n) is equal to the period T1 plus the period T2. As the period of the scan signal SCT(n) becomes longer, the frame response speed will become lower. Frame response speed refers to the response speed of a display device in displaying successive video frames. As a result of the low frame response speed, the pixel 10 cannot be applied to a display of high resolution or large size.